1. Field of the Invention
The invention relates to a downconversion system used in low intermediate frequency (IF) receivers, and more particularly to a downconversion system for low IF receivers with a high image rejection ratio (IRR) of more than 60 dB for use in analog integrated circuits (IC).
2. Description of the Related Art
With the rapid development of wireless communication and IC design technology, wireless transceiver system design and implementation has experienced great evolutions. A very high degree of integration, a low power consumption, and the use of a lower power supply are the goals set for the new development in wireless transceiver design. Although classically the heterodyne multistage intermediate frequency (IF) receiver has good performance in sensitivity and selectivity, it needs a high Q image rejection filter working in high frequency, see J. Crols and M. Steyaert, CMOS Wireless Transceiver Design, Kluwer Academic Publishers, 1997 and B. Razavi, RF Microelectronics, NJ: Prentice Hall, 1998. This component has to be external and power consumed. A Zero-IF receiver can be fully integrated and has no problem in image rejection, but it has some disadvantages such as DC offset, I/Q mismatch and cross modulation between RF and LO signal, see T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, U.K.: Cambridge Univ. Press, 1998, the J. Crols and the B. Razavi articles referred to earlier. A promising architecture is a low IF receiver, which can be fully integrated by employing some new techniques for image rejection, see the J. Crols article referred to earlier.
The low IF receiver combines the advantage of both the IF and zero IF receiver. It can achieve the good performance as well as a high degree of integration, see the Crols article referred to earlier, and    J. Crols and M. Steyaert, “A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology,” IEEE Journal of Solid State Circuits, vol. 30, no.12, pp. 1483-1492, 1995, and    J. Crols and M. Steyaert, “Low-IF Topologies for high performance analog front ends of fully integrated receivers,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 45, no. 3, pp.269-282, 1998.
The main problem of the low IF receiver is it is not easy to attain the high image rejection with this architecture, i.e. to separate well the desired RF signal from the image signal, see the J. Crols and M. Steyaert, CMOS Wireless Transceiver Design and B. Razavi articles referred to earlier. It is well known the frequency spacing between the desired RF signal and the image signal is two times the selected IF value. In the low IF receiver architecture, the selected IF is low and thus the frequency spacing between the desired RF signal and the image signal is very narrow. If the image rejection is done after low noise amplifier but before mixers, a high Q image rejection filter with very sharp transition band is needed to separate the RF signal from the image signal in high frequency. Obviously, this filter is very difficult to implement and commonly cannot be integrated. To overcome this problem, it is necessary to postpone the image rejection to a stage which is located after the downconversion mixers, and then the separation of the desired signal and image signal can be done in the low IF band.
Generally speaking, there are two methods for image rejection in a low IF receiver. One is to follow the quadrature mixers with a complex filter or a polyphase filter, see the J. Crols and M. Steyaert, CMOS Wireless Transceiver Design article referred to earlier, and F. Behbahani et al., “A 2.4 GHz low-IF receiver for wideband WLAN in 0.6 um CMOS-architecture and front-end,” IEEE Journal of State Circuits, vol. 35, no. 12, pp. 1908-1915, 2000. After downconversion by the quadrature mixers, the RF signal and the image signal will be shifted into the symmetrical positive and negative IF band, respectively. A complex filter has only a positive or negative frequency passband transfer function (selectivity) (with +fIF or −fIF as its central frequency) and thus can be used to pass the desired IF signal and reject the image IF signal at the same time, see the three articles referred to earlier:    J. Crols and M. Steyaert, “CMOS Wireless Transceiver Design”,    J. Crols and M. Steyaert, “A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology,” and    J. Crols and M. Steyaert, “Low-IF Topologies for high performance analog front ends of fully integrated receivers”.
Similarly, a polyphase filter has only a stopband in the negative or positive IF band and thus can be used to ‘trap’ the image IF signal and pass the desired signal, see the F. Behbahani article referred to earlier. The other method is to use an image rejection mixer for image rejection. The Hartley architecture and Weaver architecture are two kinds of typical image rejection mixers, see the B. Razavi article referred to earlier. The idea of image rejection mixers is to process the signal and the image differently, and cancel the image by its negated replica. This distinction between the signal and the image is possible because the two lie on different sides of LO frequency, and thus phase transformation can be explored to cancel the image signal only.
Unfortunately, the image rejection ratio (IRR) provided by either of the above methods is very sensitive to I/Q mismatch of a low IF receiver, as discussed in the J. Crols and M. Steyaert, “CMOS Wireless Transceiver Design”, B. Razavi, and J. Crols and M. Steyaert, “A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology,” articles referred to earlier. The ideal image rejection only happens in the case that the phases of I/Q local oscillator (LO) signals keep exact 90° difference and the gains of I/Q mixers are exactly equivalent. However, it is impossible to attain this perfect matching in current analog IC design process. The phase mismatch between the LOs and the gain mismatch between the mixers are inevitable. More importantly, the IRR is very sensitive to these mismatches and the image rejection performance will degrade greatly even with a small amount of mismatches, see J. C. Rudell et al., “A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications,” IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp. 2071-2088, 1997. For example, using a 4th order Butterworth complex filter for image rejection, when not any mismatch exists for I/Q Los and mixers, the IRR can attain over 77 dB. While with only 1° phase mismatch of LOs, IRR goes down to 40 dB. With 2% gain mismatch of mixers, IRR goes down to 39 dB. With 2° phase mismatch of Los and 2% gain mismatch of mixers, IRR goes down to 32 dB. Due to this reason, the currently implemented low IF receivers only can attain 30-40 dB image rejection ratio except adopting some complex trimming and tuning techniques, see C. C. Chun and C. H. Chia, “On the architecture and performance of a hybrid image rejection receiver,” IEEE Journal on Seclected Areas in Communications, vol. 19, no. 6, pp. 1029-1040, 2001. So how much image rejection is adequate? In most RF applications and by using the low IF architecture, the image signal can be 60 dB larger than the desired RF signal so that the overall IRR must be around 60 to 70 dB, see the B. Razavi article referred to earlier. The matching requirements have put a big challenge to this topology.
In the literature, several methods have been proposed to improve the IRR of low IF receivers. One is to convert the low IF signal into the baseband signal by employing bandpass delta-sigma modulator, then I/Q mismatch can be cancelled and compensated through various digital signal processing algorithms in digital domain, see Li Yu and W. M. Snelgrove, “A novel adaptive mismatch cancellation system for quadrature IF radio Receivers,” IEEE Transactions on Circuits and Systems-II: analog and Digital Signal Processing, vol. 46, no. 6, pp. 789-801, 1999, M. Valkama, and M. Renfors, “Advanced DSP for I/Q imbalance compensation in a low-IF receiver,” 2000 IEEE International Conference on Communications, vol. 2, pp. 768-772, and M. Valkama, M. Renfors, and V. Koivunen, “Advanced methods for I/Q imbalance compensation in communication receivers,” IEEE Transactions on Signal Processing, vol. 49, no.10, pp. 2335-2344, 2001. High IRR can be attained (50-70 dB) but the cost and complexity of this kind of method is also significantly increased due to the using of DSP. An interesting double quadrature mixer plus complex filter architecture is proposed in the J. Crols and M. Steyaert, “A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology,” article referred to earlier, which can achieve phase accuracy of less than 0.3 degree. Although it is a powerful way to overcome the sensitivity of IRR to phase mismatch, it still does not solve the problem of IRR sensitivity to amplitude mismatch.
Image rejection mixer and polyphase filter are used for image rejection in U.S. Pat. No. 6,127,962 (Martinson), “Image rejection mixer” and U.S. Pat. No. 6,226,509 (Mole et al.), “Image rejection mixer, circuit, and method for image rejection”, but no tuning scheme is introduced to improve the image rejection ratio in these two inventions. Quadrature mixers are used for image rejection in U.S. Pat. No. 5,937,341 (Suominen), “Simplified high frequency tuner and tuning method.” The phase mismatch and amplitude errors are corrected through a coarse stepwise tunable local oscillator and fine-tuning is performed in near baseband passband after an A/D conversion. Additional complexity has been introduced by using baseband signal compensation method. A fully integrated image rejection mixer was invented in U.S. Pat. No. 5,870,670 (Ripley et al.), “Integrated image reject mixer.” To maintain an accurate ninety degree phase difference between the quadrature IF signals, a phase detector feedback loop is employed to control the matching between the LO phase shifting network and IF phase shifting network. A radio frequency tuning circuit is used to reject image frequency in U.S. Pat. No. 4,696,055 (Marshall), “RF tuning circuit which provides image frequency rejection.” The circuit includes an N-path filter with tunable local oscillator for phase matching and a feedback loop to displace the central frequency of N-path filter from the local oscillator frequency. An image reject transceiver is invented in U.S. Pat. No. 6,137,999 (Lovelace et al.), “Image reject transceiver and method of rejecting an image” that can provide both phase and gain adjustments that causes unwanted images to be rejected. Both a phase detector circuit and an amplitude detector circuit are used to detect the I/Q mismatches. A pair of double balanced mixers are employed in an integrated IF receiver for image rejection in U.S. Pat. No. 5,140,198 (Atherly et al.), “Image canceling mixer circuit on an integrated circuit chip.” The phase shift circuit employs a specific arrangement of transistors to produce a precise 90 degree phase shift. Emitter current of the transistor is adjustable to compensate for production variations and process mismatches. In the three above cited U.S. Pat. Nos. 4,696,055, 6,137,999, and 5,140,198, to eliminate the phase mismatch between quadrature mixers, adjustable phase shifters have to be used which inevitably increase the complexity of compensation and also decrease the compensation precision. A time-shared I-Q mixer system is invented in U.S. Pat. No. 5,974,306 (Hornak et al.), “Time-share I-Q mixer system with distribution switch feeding in phase and quadrature polarity inverters” for canceling the image signal. It includes a switch assembly, polarity inverters, and clock generator. The switch assembly generates and distributes pulses which ensure the orthogonality of the in-phase and out-phase signal. A current-mode field-effect-transistor implementation ensures the gain match. A complex filter and image rejector are then used to cancel an image signal. Due to the time sharing scheme, the clock used in this invention may be very high if it is used in high frequency applications.
In this invention, quadrature mixers combined with complex filters are used for image rejection. A matching compensation technique is developed which can cancel the phase and gain mismatch before the complex filter directly in IF domain. The idea is to construct a feedback loop which can automatically detect the degree of mismatch and then eliminate them by a compensation circuits. To implement this, a correlator, a gain mismatch estimator and two variable gain amplifiers (VGA) are used in the feedback loop, which all can be integrated in analog integrated circuits. It is self-tuning and can operate in either open loop or closed loop mode. Very high IRR (>60 dB) can be attained reliably which make it a promising architecture for future wireless transceiver applications.